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HM5118160B Series
1048576-word x 16-bit Dynamic Random Access Memory
ADE-203-476 (Z) Preliminary Rev. 0.0 Dec. 6, 1995
Description
The Hitachi HM5118160B is a CMOS dynamic RAM organized as 1,048,576-word x 16-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5118160B offers Fast Page Mode as a high speed access mode.
Features
* * * Single 5 V (10%) High speed -- Access time: 60 ns/70 ns/80 ns (max) Low power dissipation -- Active mode: 935 mW/825 mW/715 mW (max) -- Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period -- 1024 refresh cycles : 16 ms : 128 ms (L-version) 4 variations of refresh -- RAS-only refresh -- CAS-before-RAS refresh -- Hidden refresh -- Self refresh (L-version) 2CAS-byte control Battery backup operation (L-version)
* *
*
* *
Note: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications. This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM5118160B Series
Ordering Information
Type No. HM5118160BJ-6 HM5118160BJ-7 HM5118160BJ-8 HM5118160BLJ-6 HM5118160BLJ-7 HM5118160BLJ-8 HM5118160BTT-6 HM5118160BTT-7 HM5118160BTT-8 HM5118160BLTT-6 HM5118160BLTT-7 HM5118160BLTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 400-mil 50-pin plastic TSOP II (TTP-50/44DC) Package 400-mil 42-pin plastic SOJ (CP-42D)
2
HM5118160B Series
Pin Arrangement
HM5118160BJ/BLJ Series VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 (Top view) 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS HM5118160BTT/BLTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 V SS I/O15 I/O14 I/O13 I/O12 V SS I/O11 I/O10 I/O9 I/O8 NC
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (Top view)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Pin Description
Pin name A0 to A9 A0 to A9 I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC Function Address input Refresh address input Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply (+5 V) Ground No connection
3
HM5118160B Series
Block Diagram
RAS RAS control circuit
UCAS UCAS control circuit
LCAS LCAS control circuit
WE WE control circuit
OE OE control circuit
I/O0
I/O0 buffer
I/O1
I/O1 buffer
I/O4
I/O4 buffer
I/O5
I/O5 buffer
Sense amp. & I/O bus
circuit
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus
I/O10 buffer
I/O10
I/O11 buffer
I/O11
Row decoder & driver
Row decoder & driver
I/O14 buffer
I/O14
I/O15 buffer
I/O15
Column decoder & driver
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus
Peripheral
Column decoder & driver
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus
I/O2
I/O2 buffer
I/O8 buffer
I/O8
Row decoder & driver
I/O3
I/O3 buffer
Row decoder & driver
I/O9 buffer
I/O9
I/O6
I/O6 buffer
I/O12 buffer
I/O12
I/O7
I/O7 buffer
I/O13 buffer
I/O13
Column address buffer
Row address buffer
Address A0 to A9
Truth Table
RAS LCAS UCAS WE OE Output Operation
4
HM5118160B Series
H L L L L L L L L L L L L L H to L H to L H to L L D L H L L H L L H L L H L H H L L L D H L L H L L H L L H L L H L H L L D H H H L L L L L L
*2 *2 *2 *2 *2 *2
D L L L D D D H H H L to H L to H L to H D D D D H
Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Word Word Word Word
Standby Read cycle
Early write cycle
Delayed write cycle
H to L H to L H to L D D D D H
Read-modify-write cycle
RAS-only refresh cycle CAS-before-RAS refresh cycle or Self refresh cycle (L-version)
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
5
HM5118160B Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Notes 1, 2 1 1
Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM5118160B -6 Parameter Operating current Standby current
*1, *2
-7 Max Min 170 2 -- --
-8 Max Min 150 2 -- -- Max Unit Test conditions 130 2 mA mA t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min
Symbol Min I CC1 I CC2 -- --
--
1
--
1
--
1
mA
Standby current (L-version) RAS-only refresh current*2
I CC2
--
150
--
150
--
150
A
I CC3
--
170
--
150
--
130
mA
6
HM5118160B Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont)
HM5118160B -6 Parameter Standby current
*1
-7 Max Min 5 --
-8 Max Min 5 -- Max Unit Test conditions 5 mA RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA
Symbol Min I CC5 --
CAS-before-RAS refresh current Fast page mode current*1, *3 Battery backup current*4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version)
I CC6 I CC7 I CC10
-- -- --
170 170 500
-- -- --
150 150 500
-- -- --
130 130 500
mA mA A
I CC11
--
300
--
300
--
300
A
Input leakage current I LI Output leakage current Output high voltage Output low voltage I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
Capacitance (Ta = 25C, VCC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable Dout.
7
HM5118160B Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *18
Test Conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5118160B -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD 110 40 10 60 15 0 10 0 10 20 15 15 60 5 15 0 0 3 Max -- -- -- -7 Min 130 50 10 Max -- -- -- -8 Min 150 60 10 Max -- -- -- Unit Notes ns ns ns
10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 15 20 15 18 70 5 18 0 0 3
10000 80 10000 20 -- -- -- -- 52 35 -- -- -- -- -- -- 50 0 10 0 15 20 15 20 80 5 20 0 0 3
10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 23 22 5 6 6 7 21 21 3 4
RAS to column address delay time t RAD t RSH t CSH t CRP t OED t DZO t DZC tT
8
HM5118160B Series
Read Cycle
HM5118160B -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD -- -- -- -- 0 0 5 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 5 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 5 40 40 0 3 3 -- -- 20 Max 80 20 40 20 -- -- -- -- -- -- -- -- 15 15 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12, 22 12 8, 9 9, 10, 17 9, 11, 17 9, 25
Write Cycle
HM5118160B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- -8 Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 23 15, 23 15, 23 14, 21 21
9
HM5118160B Series
Read-Modify-Write Cycle
HM5118160B -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 155 85 40 55 15 Max -- -- -- -- -- -7 Min 181 98 46 63 18 Max -- -- -- -- -- -8 Min 205 110 50 70 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Refresh Cycle
HM5118160B -6 Parameter Symbol Min 5 10 0 Max -- -- -- CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR RAS precharge to CAS hold time t RPC -7 Min 5 10 0 Max -- -- -- -8 Min 5 10 0 Max -- -- -- Unit Notes ns ns ns 21 22 21
Fast Page Mode Cycle
HM5118160B -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge Symbol Min t PC t RASP t CPA 40 -- -- 35 Max -- -7 Min 45 Max -- -8 Min 50 Max -- Unit Notes ns 16 9, 17, 22
100000 -- 35 -- -- 40
100000 -- 40 -- -- 45
100000 ns 45 -- ns ns
RAS hold time from CAS precharge t CPRH
10
HM5118160B Series
Fast Page Mode Read-Modify-Write Cycle
HM5118160B -6 Parameter Fast page mode read-modify-write cycle time Symbol Min t PRWC 85 60 Max -- -- -7 Min 96 68 Max -- -- -8 Min 105 75 Max -- -- Unit Notes ns ns 14, 22
WE delay time from CAS precharge t CPW
Refresh
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 16 128 Unit ms ms Note 1024 cycles 1024 cycles
Self Refresh Mode (L-version)
HM5118160BL -6 Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) CAS hold time (Self refresh) Symbol Min t RASS t RPS t CHS 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit Notes s ns ns 26
Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. (V OH = 2.4 V, VOL = 0.4 V) 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max).
11
HM5118160B Series
12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and t CPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , tCAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the I/O pin will remain open circuit (high impedance); if t OEH < tCWL, invalid data will be out at each I/O. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 20. All the V CC and VSS pins shall be supplied with the same voltages. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 23. t CWL, t DH and tDS should be satisfied by both UCAS and LCAS. 24. t CP is determined by the time that both UCAS and LCAS are high. 25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 26. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instead of tRP. 27. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 28. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024cycles of distributed CBR refresh with 15.6 s interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 29. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 30. H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) Invalid Dout
12
HM5118160B Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS Delayed write UCAS Early write LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (t CP tUL) is satisfied, fast page mode can be performed.
RAS
UCAS
LCAS t UL
4. Byte control operation by remainnig UCAS or LCAS high is guaranteed
13
HM5118160B Series
Timing Waveforms*30
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
UCAS LCAS
t ASR t RAD t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCS t RCH
WE
t DZC
t CDD
Din
High-Z
t DZO
t OEA
t OED
OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO
14
HM5118160B Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT UCAS LCAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z** * OE : H or L ** t WCS t WCS (min)
15
HM5118160B Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO
OE t OEZ t CLZ High-Z
Invalid Dout
Dout
16
HM5118160B Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
UCAS LCAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
17
HM5118160B Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP UCAS LCAS t RPC t CRP
t ASR t RAH Address Row t OFF Dout High-Z * OE, WE : H or L 18
** Refresh address : A0 - A9 (RA0 - RA9)
HM5118160B Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP UCAS LCAS t CSR t CHR t RPC t CP t CRP t CSR t CHR
Address t OFF Dout High-Z 19
* OE, WE : H or L
HM5118160B Series
Hidden Refresh Cycle
t RC t RAS
t RP
t RC t RAS
t RC t RP t RAS t RP
RAS tT t RSH t RCD
UCAS LCAS
t CHR
t CRP
t RAD tASR t RAH Address Row t ASC
t RAL t CAH
Column
t RCS WE
t RRH
t DZC High-Z Din
t CDD
t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout
t OED
t OEZ t OHO t OFF t OH
20
HM5118160B Series
Fast Page Mode Read Cycle
t RASP t CPRH t RP
RAS tT t CSH t RCD UCAS LCAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH
t RCS
t RRH t RCH
t DZC t CDD High-Z t DZO t OED
OE t RAC t AA t OEA t CAC t CLZ Dout Dout 1 t OH t CPA t AA t OHO t OEA t CPA t AA t OHO t OFF t OEZ Dout 2 t OEA t CAC t CLZ Dout N t OFF t OEZ
t OH
t OH t OHO
t OFF t CAC t OEZ t CLZ
21
HM5118160B Series
Fast Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS UCAS LCAS t PC t CP t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z** * OE : H or L ** t WCS t WCS (min)
22
HM5118160B Series
Fast Page Mode Delayed Write Cycle*18
t RASP t RP
RAS
tT t CSH t RCD
UCAS LCAS
t CP t PC t CAS t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL
t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout
High-Z
Invalid Dout Invalid Dout Invalid Dout
23
HM5118160B Series
Fast Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
UCAS LCAS
t PRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEH t WP t DZC t DS t DH Din N t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t CWL t RCS t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
24
HM5118160B Series
Self Refresh Cycle (L-version) *26, 27, 28, 29
t RP
t RASS
t RPS
RAS tT t RPC t CP UCAS LCAS t CRP t CSR t CHS
t OFF Dout High-Z 25
*Address, OE, WE: H or L
HM5118160B Series
Package Dimensions
HM5118160BJ/BLJ Series (CP-42D)
Unit: mm
27.06 27.43 Max 42 22
10.16 0.13 0.74
3.50 0.26
1
21
11.18 0.13
1.30 Max
0.43 0.10
1.27 0.10
0.80
9.40 0.25
26
2.50 0.12
+0.25 -0.17
HM5118160B Series
HM5118160BTT/BLTT Series (TTP-50/44DC)
20.95 21.35 Max 40 36
Unit: mm
50
26
1 0.27 0.07
11 15 0.13 M
25 0.80
10.16
1.15 Max 2.40 0.10 11.76 0.20 0 - 5
1.20 Max
0.13 0.05
0.145 -0.025
+0.075
0.50 0.10
27
0.68
0.80

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